# Instruction set

The aarch32 instruction set is divided into several categories, each of which serves a specific purpose. The main categories of instructions in aarch32 include:

<table><thead><tr><th width="217">Category</th><th>Description</th></tr></thead><tbody><tr><td>Data processing</td><td>Perform arithmetic and logical operations on data</td></tr><tr><td>Load/store</td><td>Move data between memory and registers</td></tr><tr><td>Control flow</td><td>Control the flow of execution in a program</td></tr><tr><td>Exception-generating</td><td>Trigger exceptions or interrupts</td></tr><tr><td>Synchronization</td><td>Manage concurrent access to shared data</td></tr><tr><td>System</td><td>Access system resources or perform other privileged operations</td></tr></tbody></table>

{% hint style="warning" %}
This is just a brief overview of some of the main instruction categories in the aarch32 ISA. There are many other instruction categories and specific instructions within each category, each of which serves a specific purpose and can be used in various ways to implement a given algorithm or program.
{% endhint %}

## Data porcessing

<table><thead><tr><th width="137">Instruction</th><th>Description</th></tr></thead><tbody><tr><td>ADD</td><td>Add two registers or a register and an immediate value</td></tr><tr><td>SUB</td><td>Subtract two registers or a register and an immediate value</td></tr><tr><td>MUL</td><td>Multiply two registers</td></tr><tr><td>DIV</td><td>Divide two registers</td></tr><tr><td>AND</td><td>Perform a bitwise AND operation on two registers or a register and an immediate value</td></tr><tr><td>OR</td><td>Perform a bitwise OR operation on two registers or a register and an immediate value</td></tr><tr><td>XOR</td><td>Perform a bitwise XOR operation on two registers or a register and an immediate value</td></tr><tr><td>NOT</td><td>Perform a bitwise NOT operation on a register</td></tr><tr><td>SHL</td><td>Shift the bits in a register to the left by a specified number of positions</td></tr><tr><td>SHR</td><td>Shift the bits in a register to the right by a specified number of positions</td></tr></tbody></table>

{% hint style="warning" %}
Note that this is not an exhaustive list of data processing instructions in the aarch32 instruction set. There are many other instructions that can be used to perform a wide range of operations on data. The specific instructions available and their exact behavior may vary depending on the implementation of the aarch32 instruction set.
{% endhint %}

## Load/Store

<table><thead><tr><th width="167">Instruction</th><th>Description</th></tr></thead><tbody><tr><td>LDR</td><td>Load a word from memory into a register</td></tr><tr><td>STR</td><td>Store a word from a register into memory</td></tr><tr><td>LDRSB</td><td>Load a signed byte from memory into a register</td></tr><tr><td>LDRSH</td><td>Load a signed half-word from memory into a register</td></tr><tr><td>LDRB</td><td>Load an unsigned byte from memory into a register</td></tr><tr><td>LDRH</td><td>Load an unsigned half-word from memory into a register</td></tr><tr><td>STB</td><td>Store a byte from a register into memory</td></tr><tr><td>STH</td><td>Store a half-word from a register into memory</td></tr></tbody></table>

{% hint style="warning" %}
Note that this is not an exhaustive list of load/store instructions in the aarch32 instruction set. There are many other instructions that can be used to load and store data from memory using a variety of addressing modes and data types. The specific instructions available and their exact behavior may vary depending on the implementation of the aarch32 instruction set.
{% endhint %}

## Control flow

<table><thead><tr><th width="135">Instruction</th><th>Description</th></tr></thead><tbody><tr><td>B</td><td>Unconditionally branch to a specified address</td></tr><tr><td>BEQ</td><td>Branch to a specified address if two registers are equal</td></tr><tr><td>BNE</td><td>Branch to a specified address if two registers are not equal</td></tr><tr><td>BL</td><td>Branch to a specified address and save the return address in a register</td></tr><tr><td>BLE</td><td>Branch to a specified address if the value in a register is less than or equal to zero</td></tr><tr><td>BLX</td><td>Branch to a specified address and switch to Thumb mode</td></tr><tr><td>BX</td><td>Branch to a specified address and switch to ARM mode</td></tr></tbody></table>

{% hint style="warning" %}
Note that this is not an exhaustive list of control flow instructions in the aarch32 instruction set. There are many other instructions that can be used to control the flow of execution in a program, such as conditional branches and subroutine calls. The specific instructions available and their exact behavior may vary depending on the implementation of the aarch32 instruction set.
{% endhint %}

## Exception-generating

<table><thead><tr><th width="164">Instruction</th><th>Description</th></tr></thead><tbody><tr><td>SVC</td><td>Trigger a supervisor call (SVC) exception</td></tr><tr><td>BKPT</td><td>Trigger a breakpoint exception</td></tr><tr><td>HVC</td><td>Trigger a hypervisor call (HVC) exception</td></tr></tbody></table>

{% hint style="warning" %}
Note that this is not an exhaustive list of exception-generating instructions in the aarch32 instruction set. There are many other instructions that can be used to trigger different types of exceptions or interrupts, such as data abort and undefined instruction exceptions. The specific instructions available and their exact behavior may vary depending on the implementation of the aarch32 instruction set.
{% endhint %}

## Synchronization

<table><thead><tr><th width="177">Instruction</th><th>Description</th></tr></thead><tbody><tr><td>DMB</td><td>Ensure that all memory accesses before this instruction have completed before any memory accesses after this instruction are performed</td></tr><tr><td>DSB</td><td>Ensure that all memory accesses before this instruction have completed before the processor can execute any subsequent instructions</td></tr><tr><td>ISB</td><td>Ensure that all instructions before this instruction have completed before any subsequent instructions are executed</td></tr></tbody></table>

{% hint style="warning" %}
Note that this is not an exhaustive list of synchronization instructions in the aarch32 instruction set. There are many other instructions that can be used to manage concurrent access to shared data by multiple threads or processes. The specific instructions available and their exact behavior may vary depending on the implementation of the aarch32 instruction set.
{% endhint %}

## System

<table><thead><tr><th width="147">Instruction</th><th>Description</th></tr></thead><tbody><tr><td>MRS</td><td>Read the value of a system register into a register</td></tr><tr><td>MSR</td><td>Write a value to a system register from a register</td></tr><tr><td>CPS</td><td>Change the current processor mode or the state of interrupts</td></tr><tr><td>SYS</td><td>Perform a privileged operation or access a system resource</td></tr></tbody></table>

{% hint style="warning" %}
Note that this is not an exhaustive list of system instructions in the aarch32 instruction set. There are many other instructions that can be used to access system resources or perform other privileged operations. The specific instructions available and their exact behavior may vary depending on the implementation of the aarch32 instruction set.
{% endhint %}