# Registers

There is 8 General Purpose Registers (GPRs) in x86 and x64 architectures.

<table><thead><tr><th width="98">x86</th><th width="95">x64</th><th width="167">name</th><th>Usage</th></tr></thead><tbody><tr><td><strong>EAX</strong></td><td><strong>RAX</strong></td><td>Accumulator</td><td>Store the results of arithmetic and logical operations</td></tr><tr><td><strong>EBX</strong></td><td><strong>RBX</strong></td><td>Base</td><td>Store the base address of memory operands</td></tr><tr><td><strong>ECX</strong></td><td><strong>RCX</strong></td><td>Counter</td><td>Store the count of iterative instructions</td></tr><tr><td><strong>EDX</strong></td><td><strong>RDX</strong></td><td>Data</td><td>Store the results of multiplication and division operations</td></tr><tr><td><strong>ESP</strong></td><td><strong>RSP</strong></td><td>Stack Pointer</td><td>Store the stack pointer</td></tr><tr><td><strong>EBP</strong></td><td><strong>RBP</strong></td><td>Base Pointer</td><td>Store the base pointer</td></tr><tr><td><strong>ESI</strong></td><td><strong>RSI</strong></td><td>Source Index</td><td>Store the source index for string operations</td></tr><tr><td><strong>EDI</strong></td><td><strong>RDI</strong></td><td>Destination Index</td><td>Store the destination index for string operations</td></tr></tbody></table>

{% hint style="info" %}
**Two groups are distinguished :**&#x20;

* **EAX/RAX, EBX/RBX, ECX/RCX and EDX/RDX** have to store temporary data for the processor.
* **ESP/RSP, EBP/RBP, ESI/RSI and EDI/RDI** are instead used as pointers and indexes
  {% endhint %}

**There is three other main registers :**&#x20;

<table><thead><tr><th width="128.33333333333331">x86</th><th width="103">x64</th><th width="116">Name</th><th>Usage</th></tr></thead><tbody><tr><td><strong>EFLAGS</strong></td><td><strong>RFLAGS</strong></td><td>Flags</td><td>Store the current state of the CPU's flags, which are special bits that are used to control the execution of instructions</td></tr><tr><td><strong>EIP</strong></td><td><strong>RIP</strong></td><td>Instruction Pointer</td><td>Store the current instruction pointer, which is the address of the next instruction to be executed by the CPU. The instruction pointer is automatically updated by the CPU as instructions are executed, and it is used to determine the order in which instructions are executed</td></tr><tr><td><strong>CS</strong></td><td><strong>CS</strong></td><td>Code Segment</td><td>Store the code segment selector, which is a value that specifies the current segment of memory that is being used to store the instructions that are executed by the CPU</td></tr></tbody></table>

{% hint style="info" %}
There is other registers like the segment registers (DS, ES, FS, GS, and SS), the control registers (CR0, CR1, CR2, CR3, and CR4), and the debug registers (DR0, DR1, DR2, DR3, DR4, DR5, DR6, and DR7). However, this is not a complete list, and there may be other registers that are available on some 32-bit x86 CPUs.
{% endhint %}


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